### Digital Circuits

Introduction to Digital Circuit Design
In most university, a very first course in digital circuit design involve nothing more than teaching number theory, boolean algebra and logic gates. From there, they will teach the concept of combinational logic, followed by sequential logic design ( synchrounous as well as asynchrounous). K-map method is often used to do logic optimization. Very often, K-map method is applied to design some combinational logic as well as some simple sequential logic design, such as a counter, state machine, etc.

In the era where digital circuits play an extremly important role in our daily life, from MP3 players, TV, cell phones, digital camera to GPS displays, complex digital circuits are integrated to perform complicated functions that are unrealizable by traditional analog circuits. One might wonders how is it possible for a designer to design a chip that consits of millions or even billions of transistors ? The answer lie in the systematic and well establised digital design flow, assited by many powerful software along the process.

While K-map and manual design will give us some good understanding on digital circuit design basics, that is not how digital circuit are designed nowadays in the industry. HDL-based design flow, where the circuits are described using hardware description language (HDL), such as VHDL and VerilogHDL language is employed in the industry to design highly complicated digital circuits.

The subsequent posts will dive in more detail on the whole digital design flow, from HDL entry to final chip layout. The most commonly used tools such as Synopsys Design Compiler, Cadence SOC encounter, and even Xilinx ISE simulator will be introduced, along with details on how to write some script to automate the design flow.

Digital ASIC design flow
The design flow of digital ASIC is quite different from analog ASIC design. While schematic entry is a normal practise in analog circuit design, digital circuit design start with HDL code entry. Various tools are used along the way to convert the HDL code into final chip layout.

In brief, the chart below summarize the standard digital ASIC design flow:

There is a  quick way to master VHDL language by refering to relevant example and do the modification accordingly. To begin, let's review some characteristics of VHDL language. Unlike any other high level programming language such as C or Java, VHDL is a hardware description language, compiled into logic primitives consists of logic gates realised by transistors. Since it is a hardware description language, it consists of concurrent statements to describle hardware parallel execution nature. VHDL is case insensitive.
Some simple examples to be described here includes:

More examples to be updated.

1. 3-bit MUX. Notice that VHDL is case insensitive, so it is perfectly ok to combine upper-case or lower case in the description.
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY mux8to1 IS
PORT (a0, a1, a2, a3, a4, a5, a6, a7, a8 : IN STD_LOGIC;
p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
m : OUT STD_LOGIC);
END mux8to1;
ARCHITECTURE Behaviour OF mux8to1 IS
BEGIN
WITH P SELECT
m<=a0 WHEN "000",
a1 WHEN "001",
a2 WHEN "010",
a3 WHEN "011",
a4 WHEN "100",
a5 WHEN "101",
a6 WHEN "110",
a7 WHEN others,
END Behaviour;
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2. Counter . Unlike previous combinational logic, this example will illustate a simple sequential logic circuit, such as a 3-bit up counter
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY counter3 is
port(rst,clk : in std_logic;
Cntout : out std_logic_vector(2 downto 0));
end counter3;

architecture Beh_counter3 of counter3 is
signal temp_cnt : std_logic_vector(2 downto 0);
begin
process(clk, rst,)
begin
if rst='1' then
temp_cnt<= "000";
elsif  clk'event and clk='1' then
temp_cnt <= temp_cnt + '1';

end if;
end if;
end process;
Cntout <= temp_cnt;
end Beh_counter3;
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